1. Field of the Invention
The present invention relates to a semiconductor memory device and fabricating method thereof, and more particularly to a non-volatile memory device and fabricating method thereof.
2. Description of the Related Art
Generally, semiconductor memory device may be classified into volatile memory device and non-volatile memory device. When power supply is interrupted, the data stored in the volatile memory device will disappear, while the data stored in the non-volatile memory device will still be stored. That is to say, the volatile memory device has the property that is the memory will disappear as the power is off. Therefore as the power supplied is discontinuous or interrupted frequently, or the element is an electronic element that requires low voltage only, such as memory card of the digital camera, portable disk, mobile phone, the non-volatile memory device is commonly used to store the data. As a result, the non-volatile memory device plays a very important role in the convenience-oriented modern society.
For the non-volatile memory device, the storage of data is achieved by two ways: one is by a floating gate device and the other is by a charge trapping device.
As shown in FIG. 1, a non-volatile memory device using the floating gate device is illustrated, which has a floating gate device 110 under a gate 120. Its memory is conducted by storing the electrons on a floating gate 112 that is a good conductive material, so that the electrons trapped on the floating gate 112 are distributed uniformly thereon, such that the thresh voltage generates a shift upon which determines whether memorize or not. However, the floating gate device can only store one bit, causing the production cost raised, so it cannot meet the economic efficiency.
With reference to FIG. 2, a non-volatile memory device using the charge trapping device is illustrated, which has a charge trapping device 210 stacked to two or three layers under a gate 220, and in which there is a charge trapping layer 212 with high deep-level trap density. The high deep-level trap density is an insulating material that can catch electrons, for example, Si3N4 or Al2O3, so the electrons can be caught effectively to store charges. However, since the bottom of the charge trapping device 210 is an oxide layer 214, in which the positive charges are trapped during erasing, causing the barrier of the oxide layer 214 reduced, the electrons trapped in the charge trapping layer 212 can easily tunnel through the oxide layer 214, causing the loss of electrons, and therefore the storage time is reduced. And conventionally, the charge trapping layer used to store charges is a single-layer structure, so its modulation for storing charge is not high. In recent years, the thickness of the oxide layer is reduced in order to increase the quantity of the stored charges, and further to increase the electric leakage.
Accordingly, for the non-volatile memory device by means of the charge trapping device, there is still a space for improvement.